規格
| 屬性 | 價值 |
| Supplier | Microchip Technology |
| Package / Case | Tray |
| Part Status | Active |
| PLL | Yes |
| Main Purpose | SONET/SDH, Stratum |
| Input | LVCMOS |
| Output | LVCMOS, LVPECL |
| Number of Circuits | 1 |
| Ratio - Input: Output | 11:12 |
| Differential - Input: Output | No/Yes |
| Frequency - Max | 622.08MHz |
| Voltage - Supply | 2.97V ~ 3.63V |
| Operating Temperature | -40°C ~ 85°C |
| Mounting Type | Surface Mount |
概述
Description
Pinout
Pin count: 28 pins (in the ZL30121GGG2V2 package).
Function: A programmable clock synthesizer/PLL with jitter attenuation used to generate and condition clean reference clocks for high-speed serial interfaces (SERDES, SONET/SDH, etc.).
Function: A programmable clock synthesizer/PLL with jitter attenuation used to generate and condition clean reference clocks for high-speed serial interfaces (SERDES, SONET/SDH, etc.).
Manufacturer
Manufacturer: Zarlink Semiconductor (Zarlink).
What kind of company: A semiconductor company specializing in mixed-signal/analog ICs for telecommunications networks; originally Canadian, later acquired and integrated into Broadcom's semiconductor business.
What kind of company: A semiconductor company specializing in mixed-signal/analog ICs for telecommunications networks; originally Canadian, later acquired and integrated into Broadcom's semiconductor business.
Package
QFN package, typically 28 pins (about 6×6 mm) for the ZL30121GGG2V2 variant per Zarlink’s datasheet.
